add_subdirectory(AffineToLoopSchedule)
add_subdirectory(AIGToComb)
add_subdirectory(ArcToLLVM)
add_subdirectory(CalyxToFSM)
add_subdirectory(CalyxToHW)
add_subdirectory(CombToAIG)
add_subdirectory(CombToArith)
add_subdirectory(CombToLLVM)
add_subdirectory(CombToSMT)
add_subdirectory(ConvertToArcs)
add_subdirectory(DCToHW)
add_subdirectory(ExportChiselInterface)
add_subdirectory(ExportVerilog)
add_subdirectory(FIRRTLToHW)
add_subdirectory(FSMToSV)
add_subdirectory(HandshakeToDC)
add_subdirectory(HandshakeToHW)
add_subdirectory(HWArithToHW)
add_subdirectory(HWToBTOR2)
add_subdirectory(HWToLLVM)
add_subdirectory(HWToSMT)
add_subdirectory(HWToSV)
add_subdirectory(HWToSystemC)
add_subdirectory(LoopScheduleToCalyx)
add_subdirectory(MooreToCore)
add_subdirectory(PipelineToHW)
add_subdirectory(SCFToCalyx)
add_subdirectory(SeqToSV)
add_subdirectory(SimToSV)
add_subdirectory(CFToHandshake)
add_subdirectory(VerifToSMT)
add_subdirectory(SMTToZ3LLVM)
add_subdirectory(VerifToSV)
add_subdirectory(CalyxNative)
add_subdirectory(LTLToCore)

if(CIRCT_SLANG_FRONTEND_ENABLED)
  add_subdirectory(ImportVerilog)
endif()
